In the manufacture of semiconductor products such as integrated circuits, individual electrical devices are formed on or in a semiconductor substrate, and are thereafter interconnected to form electrical circuits. Interconnection of these devices within an integrated circuit is typically accomplished by forming a multi-level interconnect network in layers formed over the electrical devices, by which the device active elements are connected to one another to create the desired circuits. Individual wiring layers within the multi-level network are formed by depositing an insulating or dielectric layer over the discrete devices or over a previous interconnect layer, and patterning and etching cavities such as vias and trenches. Conductive material, such as copper is then deposited into the cavities and the wafer is planarized using chemical mechanical polishing (CMP) to form an interconnect structure.
Typical interconnect structures are fabricated using single or dual damascene processes in which trenches and vias are formed (etched) in dielectric layer. Copper is then deposited into the trenches and vias and over the insulative layer, followed by CMP planarization to leave a copper wiring pattern including the desired interconnect metal inlaid within the dielectric layer trenches. The process may be repeated to form further interconnect layers or levels by which the desired circuit interconnections are made in a multi-level interconnect network.
Etch-stop layers are often formed beneath the dielectric material layers to provide controlled stopping of the via and/or trench formation etch processes. Silicon nitride (SiN) is typically employed as an etch stop material, although recently silicon carbide (SiC) has also been used for etch stop layers in interconnect processing. Diffusion barriers are often formed in the damascene cavities prior to deposition of copper to mitigate diffusion of copper into the dielectric material. Such barriers are typically formed using conductive compounds of transition metals such as tantalum nitride, titanium nitride and tungsten nitride, as well as the various transition metals themselves. Conductive metals, such as aluminum, copper, or the like are then used to fill the cavities after barrier layer formation, where copper is gradually replacing aluminum to improve the conductivity of the interconnect circuits.
To reduce or control RC delay times in finished semiconductor products, recent developments have focused on low dielectric constant (low-k) dielectric materials for use between the metal wiring lines, in order to reduce the capacitance therebetween and consequently to increase circuit speed. Examples of low-k dielectric materials include spin-on-glasses (SOGs), as well as organic and quasi-organic materials such as organo-silicate-glasses (OSGs), for example, having dielectric constants (k) as low as about 2.6-2.8, and ultra low-k dielectrics having dielectric constants below 2.5. OSG materials are low density silicate glasses to which alkyl groups have been added to achieve low-k dielectric characteristic.
Single and dual damascene processes using OSG, FSG, or ultra-low k dielectric materials, SiC material, and copper fill metals can thus be employed to increase speed, reduce cross talk, and reduce power consumption in modern high-speed, high-density devices. However, incorporating these materials into workable semiconductor fabrication processes presents additional challenges. Etch processes used to remove various layers in an etch stack, including SOG layers, underlayers, dielectric layers, the etch-stop material beneath the dielectric layer or layers, and the like, often leave polymer residue on various areas of the wafer surface, including, among others, on the dielectric sidewalls and the bottom of the trench or via cavities, which must be cleaned or removed prior to barrier formation and filling.
This residual polymer, if left uncleaned, causes a high resistance interface between underlying conductive features and the deposited fill or barrier material, thus exacerbating RC delays. However, the cleaning process itself must not corrode or damage the underlying conductive feature to which connection is to be made. Further, the cleaning process should not change the dimensions of the cavities. Wet cleaning processes have been used in the past to remove polymers formed on oxide type dielectric sidewalls when etching through SiN type etch-stop layers. Thus, there remains a need for fabricating single and/or dual damascene interconnect structures in semiconductor wafers by which these and other adverse effects can be mitigated or overcome, without negatively impacting production costs or cycle times.